Module 1: Introduction to VLSI

• VLSI overview: very large scale integration and IC design industry
• VLSI design flow: RTL design, synthesis, place and route, and signoff
• ASIC vs FPGA: design approaches and trade-offs
• CMOS fundamentals: nMOS, pMOS, and CMOS inverter operation

Module 2: Verilog HDL Fundamentals

• Verilog basics: modules, ports, and wire/reg data types
• Combinational logic: assign statements and continuous assignments
• Sequential logic: always blocks, blocking, and non-blocking assignments
• Structural modelling: instantiating and connecting modules

Module 3: RTL Design with Verilog

• Finite State Machines: Mealy and Moore FSM coding in Verilog
• Arithmetic circuits: adders, subtractors, multipliers, and dividers
• Memory elements: registers, FIFOs, and SRAM models
• Parameterised designs: scalable RTL with parameter and localparameter

Module 4: SystemVerilog for Design

• SystemVerilog enhancements: logic type, always_ff, always_comb
• Interfaces: bundling signals for cleaner module connections
• Packages: shared type definitions and parameter collections
• Assertions: immediate assertions for design intent documentation

Module 5: Functional Verification

• Verification fundamentals: testbench structure and coverage goals
• SystemVerilog testbench: classes, randomisation, and constraints
• UVM (Universal Verification Methodology): overview and component hierarchy
• Coverage: code coverage and functional coverage metrics

Module 6: Logic Synthesis

• Synthesis flow: RTL to gate-level netlist with Design Compiler
• Timing constraints: clock definition, input/output delays, and false paths
• Area and power optimisation: synthesis directives and trade-offs
• Gate-level simulation: verifying netlist against RTL behaviour

Module 7: FPGA Implementation

• FPGA architecture: LUTs, flip-flops, DSPs, and BRAMs
• Xilinx Vivado or Intel Quartus: FPGA design flow
• Constraints: XDC or SDC timing and pin assignment
• FPGA debugging: Integrated Logic Analyser (ILA) and SignalTap

Module 8: Capstone Project and Assessment

• RTL design: processor datapath or communication controller in Verilog
• UVM testbench: constrained-random verification environment
• FPGA implementation: synthesise, implement, and verify on FPGA board
• Final assessment and course certification

Experience in the Industry Gain expertise from VLSI design and verification engineers who have worked on ASIC and FPGA designs for semiconductor companies, communications, networking, and consumer electronics chip development.

Backgrounds at the Top Our VLSI trainers have worked at fabless semiconductor companies, IP development firms, and VLSI design service organisations delivering RTL design, verification, and FPGA implementation projects.

Clear & Effective Teaching VLSI design flow, Verilog and SystemVerilog RTL design, FSM coding, UVM verification, logic synthesis, timing constraints, FPGA implementation, and FPGA debugging are explained with real IC design examples.

Hands-On Learning Focus Students write Verilog RTL, build UVM testbenches, run synthesis with timing constraints, implement designs on FPGA, and debug with ILA through structured hands-on VLSI design and verification labs.

Up-to-Date Knowledge Trainers keep content current with the latest EDA tool releases from Synopsys, Cadence, and Xilinx/AMD, UVM 1.2 methodology updates, and evolving digital IC design and verification best practices.